1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a trimming method of a semiconductor integrated circuit device and, for example to a semiconductor integrated circuit device having a sense amplifier with a trimming function and a trimming method of the same.
2. Related Art
In a semiconductor memory device typified by an SRAM (Static Random Access Memory) and the like, a potential difference between paired bit lines according to data of a memory cell is amplified by a sense amplifier, and the potential difference is output as data. Generally, a sense amplifier is constructed with a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) in consideration of the low power consumption characteristic and the like. The sense amplifier constructed with a MOSFET has an offset voltage. The offset voltage is the minimum potential difference between paired bit lines necessary for the sense amplifier to output correct data. To correctly output data of a memory cell, the sense amplifier has to wait to perform operation of amplifying a potential difference (signal difference) between paired bit lines until the potential difference increases to the offset voltage or higher. Consequently, when the offset voltage is high, the operation speed of the sense amplifier decreases, and reading operation of the semiconductor memory device becomes slow. The operation speed of the semiconductor memory device depends on not only the operation speed of the memory cell but also the operation speed of the sense amplifier.
To address the problem, a method of trimming the offset voltage of the sense amplifier is considered. A conventional sense amplifier has two trimming transistors provided between two current paths, which are corresponding to each of paired bit lines or each of paired sense nodes, and a power supply, and two latch circuits for turning on/off the trimming transistors. To reduce variations in the offset voltage, the latch circuits turn on one of the two trimming transistors and turn off the other trimming transistor, thereby adjusting amounts of current flowing through the two current paths. The trimming amount of the offset voltage is a predetermined value determined by the size (W/L) of a trimming transistor, that is, current drivability.
However, when such a trimming method is employed, although variations in the offset voltage are reduced the offset voltage of sense amplifiers around an expectation value (offset voltage=0) is also trimmed, so that the number of offset voltages of the sense amplifiers existing at ends of a distribution of the offset voltage increases as shown in FIG. 5. Further, since there are also variations among the trimming transistors, a distribution of the offset voltages is widened in such a manner that both ends of the distribution are elongated.
In addition, in the conventional semiconductor memory device, to maintain symmetry of a sense amplifier, a trimming transistor, a latch circuit, a buffer circuit, and the like have to be provided for each of two sense nodes. It causes a problem such that the size of the semiconductor memory device as a whole becomes large.